Thus, our machine is closer to a superpipelined machine of degree two than it is to our ideal base
machine. To the extent that some operation latencies are greater than one base machine cycle,
the remaining amount of exploitable instruction-level parallelism will be reduced. In this
example, assuming the average degree of instruction-level parallelism in slightly parallel code is
around two, this machine should not stall often because of data-dependency interlocks.