Read and Write commands to a bank can only take place to locations within one row at a time, which must be first copied into the bank’s row buffer (Activate command). Prior to accessing a different row, the one currently stored in the row buffer must be written back to its permanent location (Precharge command). Finally, since DRAM is nonpersistent, rows need to be periodically read out and restored to maintain data integrity (Refresh command). To make matters more difficult, modern DRAM chips have a large number of timing constraints that must be obeyed when scheduling commands, which any memory scheduler must work around.