This paper describes an Itanium processor implemented
in 65 nm process with 8 layers of Cu interconnect. The
21.5 mm by 32.5 mm die has 2.05B transistors. The processor has
four dual-threaded cores, 30 MB of cache, and a system interface
that operates at 2.4 GHz at 105 C. High speed serial interconnects
allow for peak processor-to-processor bandwidth of 96 GB/s and
peak memory bandwidth of 34 GB/s.
Index Terms—65-nm process technology, circuit design, clock
distribution, computer architecture, microprocessor, on-die cache,
voltage domains.