Fig. 2. Internal blocks of the core include axons (A), crossbar synapses
implemented with SRAM, axon types (G), and neurons (N). An incoming
address event activates axon 3, which reads out that axon’s connections, and
results in updates for neurons 1, 3 and M.
Based on these considerations, we arrived at a block-level
implementation of our neurosynaptic core that consists of
an input decoder with 1024 axon circuits, a 1024 × 256
SRAM crossbar, 256 neurons, and an output encoder (Fig. 2).
Communication at the input and output of the core follows
an address-event representation (AER), which encodes binary
activity, such as A(t), by sending the locations of active
elements via a multiplexed channel [4]. For each time step,
the detailed operation of the core commences in two phases:
the first phase implements the axon-driven component, and the
second phase implements a time step synchronization.
In the first phase, address-events are sent to the core one
at a time, and these events are sequentially decoded to the
appropriate axon block (e.g., axon 3 from Fig. 2). On receiving
an event, the axon activates the SRAM’S row, which reads
out all of the axon’s connections as well as its type. All
the connections that exist (all the 1’s) are then sent to their
respective neurons, which perform the appropriate membrane
potential updates; the 0’s are ignored. After the completion
of all the neuron updates, the axon block de-asserts its read,
and is ready to process the next incoming address event; this
continues until all address events for the current time step are
serviced.
In the second phase, which occurs once every millisecond,
a synchronization event (Sync) is sent to all the neurons. On
receiving this synchronization, each neuron checks to see if it