Endurance Implications. With a read-only DRAM cache, all memory writes are directed to PCM, which may seem to contravene conventional wisdom. But cache blocks are less often re-used after last-level cache eviction, which means processor SRAM caches have already exploited opportunities for write coalescing. Writing multiple times to the same block in the DRAM cache, the case in which using read-only DRAM would harm PCM endurance, is not common.