CLOCKED D FLIP-FLOPS
The RS Flip-Flop has two data inputs, R and S. To store a high bit, you need a high S; to store a low bit, you need a high R. Generation of two signals to drive a flip-flop is a disadvantage in many applications. Furthermore, the forbidden condition of both R and S high may occur inadvertently. This has led to the D flip-flop, a circuit that needs only a single data input.
Figure 8-14 shows a simple way to build a D (Data) flip-flop. This flip-flop is disabled when EN is low, but is transparent when EN is high. The action of the circuit is straightforward, as follows. When EN is low, both AND gates are disabled; therefore, D can change value without affecting the value of Q. On the other hand, when EN is high, both AND gates are enabled. In this case, Q is forced to equal the value of D. When EN again goes low, Q retains or stores the last value of D.
There are many ways to design D flip-flops. In general, a D flip-flop is a bistable circuit whose D input is transferred to the output when EN is high. Figure 8-15 shows the logic symbols used for any type of D flip-flop.
In this section we’re talking about the kind of D flip-flop in which Q can follow the value of D while EN is high. In other words, if the data bit changes while EN is high, the last value of D before EN returns low is the value of D that is stored. This kind of D flip-flop is often called a D latch.
Figure 8-15b shows the truth table for a D latch. While (EN) is low, D is a don’t care (X); Q will remain latched in its last state. When EN is high, Q takes on the last value of D. If D is changing while EN is high, it is the last value of D that is stored.
The idea of data storage is illustrated in Figure 8-16. Four D latches are driven by the same clock signal. When the clock goes high, input data is loaded into the flip-flops and