An architecture’s memory consistency model [1]
specifies the interface between the shared memory system and the software. It specifies the allowable software-visible interleavings of the memory operations
(loads, stores, and synchronization operations) that are
performed by the multiple threads. For example, SC
specifies that there exists a total order of memory operations that maintains the program orders of all threads
[12]. Other consistency models are less restrictive than
SC, and they differ in how they permit memory operations to be reordered between program order and the
order in which the operations perform. These reorderings are only observed by other processors, but not by
the processor executing them due to the in-order program execution model.