FIG. 11A is a circuit diagram shoWing the con?guration of the ramp signal generating circuit 3 for preventing the above described situation. A sWitch S3 is, for example, a
transistor. An inverter 13 is connected to a control terminal of the sWitch S3 so that the sWitch S3 is turned off if the pulse signal from the oscillator 2 is H, and is turned on if the pulse signal is L as shoWn in FIG. 11B. While the sWitch S3 is in the OFF state, the capacitor Cx is gradually charged. In the meantime, While the sWitch S3 is in the ON state, the capacitor Cx is discharged by the electric current ?oWing via
the sWitch S3. Therefore, assuming that the resistance of the path reaching from the node B to the ground via the sWitch S3 is 0 in the above described circuit, the ramp signal Ramp3 is driven to the electric potential of the ground on the falling edge of the pulse signal from the oscillator 2. This electric potential is sure to be held until the timing at Which the latch circuit 5 is set. Namely, the ramp signal Ramp3 is sure to be held to the electric potential of the ground during a prede termined time period immediately before the latch circuit 5 is set. As described above, there is alWays a lag betWeen the timing at Which the ramp signal Ramp3 is started to be discharged and the timing at Which the latch circuit 5 is set