Chapter 7 / Counters and Registers
The PRESENT to the NEXT state , because it is an independent input that is held HIGH or LOW as the counter goes through is sequence.
Steps 5 of the design process is presented in figure 7-38 where the information in Table 7-6 has been transferred to the K maps showing how each J and K signal is related to the PRESNET states of D, B, and A. Using the appropriate looping, the simplified logic expressions for each J and K signal are obtained.
FIGURE 7-38 (a) K maps for JB and KB (b) K maps for JA and KA