CVAX was intended to advance the MicroVAX family by providing 2.5X the performance of MicroVAX at lower power. It incorporated a number of microarchitectural advances, including an autonomous, state-machine driven instruction parser; on-chip first level cache; explicit support for an off-chip, second level cache; and a "half-folded" (register writes overlapped with register reads) pipeline. The companion floating point unit, CFPA, likewise advanced on the MicroVAX FPU by incorporating wider shifters and a better multiplier.