In a digital circuit, it always takes a certain period of time for
the output of each gate to respond to the eventS at its inputs.
In a VHDL program, we should indicate the amount of
propagation delay for an event on each signal. In the above
example, input events on signals A,B, and C produce events
on the internal signals (AB) and (BC).
Events on signal (AB)
produce events on (AB)'. Finally, events on internal signals
(AB)' and (BC) will produce events on the output signal X.
Thus, there are three signals (AB), (AB)', and (BC) in our
digital circuit as shown in figure (2).