2.Problem formulation
Floorplaning is the partitioning of the entire chip area into smaller rectangles which will be occupied by the various given building blocks. In the case of a microprocessor, these building blocks (also called modules) are such as instruction cache, instruction decode unit, integer arithmetic and logic unit, and alike. When deciding on a flooplan, we take into account the preferred mutual position of the modules, which is determined by the number of nets that connect them. Two modules which have a large number of common nets should be placed as close as possible in order to reduce the total wiring length and obtain a high performance design by reducing the communication delays among the modules. Since at the flooplanning phase the complete routing has not been attempted, only estimates of the wiring length can be taken into account.