1.3.3 Limitations of Way-Prediction Schemes
Way-prediction designs have been proposed for fast L1 caches.
There are several reasons for which the original way-prediction
idea cannot be applied directly to large L2 caches.
First, in way-prediction designs, the predicted way number must
be made available before the actual data address is generated. We call this an out-cache1 feature for way-prediction designs.
As large L2 caches are typically physically-indexed caches, a
virtual to physical address translation must be conducted before the
address can be presented to the way-prediction hardware. The wayprediction
mechanism sitting between the TLB and the L2 cache
will add extra delay to the critical path. Second, L2 caches are
unified caches, where most of the references come from L1 data
cache misses. MRU based prediction does not always work well