3.3. Simulation results and discussion
Fault simulation is performed at circuit level, i.e. all
logic gates and Op Amps are flattened to transistor
level. A total of 156 single short and open faults of
the self-testable FRWC are simulated. For each
injected fault, the response is recorded and analyzed.
Our results have shown that 6 out of 156 single
faults were not detectable. However, further
investigations revealed that this set of undetectable
faults could be detected if other test technique (for
example, IDDQ measurement) other than voltage-based
test method was used.
4. CONCLUSIONS AND FUTURE WORK
An effective self-testable full range window
comparator has been presented. Due to the built-in
fault tolerant features of the self test circuitry, veryhigh fault coverage of the FRWC is assured. The
major advantages of the proposed self-testable design
are that it is easy to implement and it has small
hardware overhead.
As is reported in [2], the use of FRWC could be
an effective means to test and diagnose embedded
functional cores with minimum hardware overhead
and I/O pins. In future we would like to extend the
use of the self-testable FRWC to the testing of
embedded mixed-signal cores in SOC designs.
3.3. Simulation results and discussionFault simulation is performed at circuit level, i.e. alllogic gates and Op Amps are flattened to transistorlevel. A total of 156 single short and open faults ofthe self-testable FRWC are simulated. For eachinjected fault, the response is recorded and analyzed.Our results have shown that 6 out of 156 singlefaults were not detectable. However, furtherinvestigations revealed that this set of undetectablefaults could be detected if other test technique (forexample, IDDQ measurement) other than voltage-basedtest method was used.4. CONCLUSIONS AND FUTURE WORKAn effective self-testable full range windowcomparator has been presented. Due to the built-infault tolerant features of the self test circuitry, veryhigh fault coverage of the FRWC is assured. Themajor advantages of the proposed self-testable designare that it is easy to implement and it has smallhardware overhead.As is reported in [2], the use of FRWC could bean effective means to test and diagnose embeddedfunctional cores with minimum hardware overheadand I/O pins. In future we would like to extend theuse of the self-testable FRWC to the testing ofembedded mixed-signal cores in SOC designs.
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