There are a couple of options to support selective control of DRAM chips. One is to route individual CS and CKE signals through unused pins of DIMM from the memory controller. The other option can be implemented in the register of DIMM (RDIMM and LRDIMM) by using the address bus to deliver individual CS and CKE signals and by address decoding mechanism. The first option is limited
to UDIMM with x8 chips because unused pins are insufficient in UDIMM with x4 chips, RDIMM, and LRDIMM. Since off-chip capacity and signal integrity of pins are one of the tightest constraints in modern DRAM system design, we choose the second option to realize SDS. Such an implementation approach also can be found in the sub-rank memory organization (register/demux architecture).