In addition to assisting silicon debug, the DVM output
provides a continuous frequency measurement during the
microprocessor operation. An adaptive clock control circuit
interfaces with the DVM to dynamically adjust FCLK by
changing the PLL divide ratio in response to dynamic
variations. Since the DVM directly maps multiple dynamic
variations into a single path-level frequency change, the DVM
guides the adaptive clock control with the desired FCLK value.
A demonstration of the adaptive clocking highlights the DVM
capability to maximize efficiency within the presence of
dynamic variations.