The DDWB consists of a 256KB space used to hide the
write latency to the NVRAM. The DDWB stores only the dirty cache blocks among the
reusable-blocks evicted from the DDCB, and so the data can be selectively written in
cache block size units (64Bytes). The DDWB is managed according to FIFO protocol.
Thus, dirty cache blocks are only written back to the NVRAM when they are evicted
from the DDWB. Because of the DDWB, dynamic data can pass through up to three
levels of buffer hierarchy, allowing greater delays for write operations. The DDWB
includes a write queue and so can provide requested data concurrently.