Over the next decade, semiconductor device
technology will continue to reflect and track Moore’s
Law until the effects of nanoscale feature size, near
the atomic limit force a cessation of continued
reduction in device size. Even though this eventual
“flat-lining” of Moore’s law will block continued
expansion of device density beyond a certain limit,
the extremes in technology scale and clock rate will
demand innovations in architecture as dramatically
different structures and operational modes will be
required to effectively utilize achievable nanoscale
technology.