3
cycles/instruction for infinite cache, and the average number
of bus cycles of a bus transaction, with a given line size, in an
N-way MP is assumed to be the same as in a 2-way MP. The
last assumption is because that we only have 2-way MP traces
available. Several important facts can be observed in this table. First, in a 4-way MP, a 32KB cache can incur 4.5 times
as much MP degradation as a 128KB cache. Secondly, although a line size of 128-Byte can attain a higher cache hit
ratio, it incurs a higher MP degradation because the average
time for a bus transaction becomes longer. Third, the UP
configuration with a 128KB store-in cache can be expanded
to a 4-way MP with acceptable degradation, less than 20%,
due to bus contention.