3.2. Half-active DRAM
Figure 7 shows the logic views of various Half-DRAM designs.
By leveraging the column select line (CSL) gate shown
in Figure 7a, fine-grained activation can be easily enabled in
1RD-2HFF as the Even group is active while the Odd group is
idle, or vice versa. The MSB of column address is used to determine
which half of a bank should be activated. The posted-
CAS technique allows ACT and CAS commands to be issued
back-to-back, which can be leveraged in this work to know the
column address in advance. Once such fine-grained activation
is applied to commodity DRAM, only half of a DRAM chip