However, direct—mapped caches tend to have lower hit rates than fully associative caches, due to conflicts between lines that map into the same space in the cache. Each address can only be placed in one location in the cache, which is determined by the m address bits illustrated in Fig. 5. If two addresses have the same value in those bits, they map onto the same line in the cache and cannot reside in the cache at the same time. A program that alternated between references to these two addresses would never hit in the cache, since the line containing each address would always have been evicted before the next reference to the address. Thus, the cache could achieve a 0 percent hit rate, even though the program only referenced two addresses. In practice, direct-mapped caches, particularly large direct-mapped caches, can achieve good hit rates, although their hit rates tend to be lower than those caches that provide multiple possible locations for each cache line.
However, direct—mapped caches tend to have lower hit rates than fully associative caches, due to conflicts between lines that map into the same space in the cache. Each address can only be placed in one location in the cache, which is determined by the m address bits illustrated in Fig. 5. If two addresses have the same value in those bits, they map onto the same line in the cache and cannot reside in the cache at the same time. A program that alternated between references to these two addresses would never hit in the cache, since the line containing each address would always have been evicted before the next reference to the address. Thus, the cache could achieve a 0 percent hit rate, even though the program only referenced two addresses. In practice, direct-mapped caches, particularly large direct-mapped caches, can achieve good hit rates, although their hit rates tend to be lower than those caches that provide multiple possible locations for each cache line.
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