Whether or not a system has memory-mapped I/O, its CPU needs to address the device controllers to exchange data with them. The CPU can request data from an I/O controller one byte at a time but doing so for a device like a disk that pro- duces a large block of data wastes the CPU's time, so a different scheme, called DMA(Direct Memory Access) is often used. The operating system can only use DMA if the hardware has a DMA controller, which most systems do. Sometimes this controller is integrated into disk controllers and other controllers, but such a design requires a separate DMA controller for each device. More commonly, a single DMA controller is available(e.g., on the parentboard) for regulating trans fers to multiple devices, often concurrently No matter where it is physically located, the DMA controller has access to the system bus independent of the CPU, as shown in Fig. 3-4. It contains several registers that can be written and read by the CPU. These include a memory address register, a byte count register, and one or more control registers. The con trol registers specify the LO port to use, the direction of the transfer(reading from the I/O device or writing to the I/O device), the transfer unit(byte a a time word at a time), and the number of bytes to transfer in one burst. To explain how DMA works, let us first look at how disk reads occur when DMA is not used. First the controller the(one or more sectors) from the drive serially, bit by bit, until the entire block is in the controller's internal ffer. Next, it computes the checksum to verify that no read errors have oc curred. Then the controller causes an interrupt. When the operating system starts