Next, we implemented the same design using the Pull– Model. Again, there is a simulation object modeling each of the various logic components of the LC3. Synchronous devices register with a master clock to be notified on each clock tick event, both rising edge and falling edge. However, with this design, we do not schedule “input changed” events to neighbors as above. On each clock tick, the synchronous devices determine if they in fact need to know their current value or not. For example, a register device does not latch its inputs unless the corresponding enable signal is asserted. For the PC register,the input value is only significantif the LD.PC enable signal is a one. If the input value is in fact relevant, the device asks the originator of the input what the correct current value is. This frequently results in transitive requests for input values, as asynchronous devices will need to ask for their current inputs to determine the output value