There are numerous models available to illustrate
how the MOSFET works, nevertheless finding
the right representation might be difficult. Most
of the MOSFET manufacturers provide Spice
and/or Saber models for their devices, but these
models say very little about the application traps
designers have to face in practice. They provide
even fewer clues how to solve the most common
design challenges.
A really useful MOSFET model which would
describe all important properties of the device
from an application point of view would be very
complicated. On the other hand, very simple and
meaningful models can be derived of the
MOSFET transistor if we limit the applicability
of the model to certain problem areas.
The first model in Figure 2 is based on the actual
structure of the MOSFET device and can be used
mainly for DC analysis. The MOSFET symbol in
Figure 2a represents the channel resistance and
the JFET corresponds to the resistance of the
epitaxial layer. The length, thus the resistance of
the epi layer is a function of the voltage rating of
the device as high voltage MOSFETs require
thicker epitaxial layer.
Figure 2b can be used very effectively to model
the dv/dt induced breakdown characteristic of a
MOSFET. It shows both main breakdown
mechanisms, namely the dv/dt induced turn-on of
the parasitic bipolar transistor - present in all
power MOSFETs - and the dv/dt induced turn-on
of the channel as a function of the gate
terminating impedance. Modern power
MOSFETs are practically immune to dv/dt
triggering of the parasitic npn transistor due to
manufacturing improvements to reduce the
resistance between the base and emitter regions.
It must be mentioned also that the parasitic
bipolar transistor plays another important role. Its
base – collector junction is the famous body
diode of the MOSFET.