The power consumption reduction has been achieved with an extremely careful design both at system and at circuit level of the overall PLM. Analog and digital worlds are widely used and the signal is converted several times in its processing in order to optimize the power consumption. Notice that alternative solutions with the same dynamic range over the same bandwidth (=lOOkHz) results in architecture using XA solutions. These approaches require a large OSR and so a large sampling frequency and a large power consumption.