Memory AddressingThe instruction set shall use 16-bit logical addresses to provide for referencing of65,536 words. When the expanded memory option (see Section 4.5.2, “ExpandedMemory Addressing (optional)” [27]) is not implemented, physical addresses shallequal logical addresses.4.5.1.1. Memory Addressing ArithmeticArithmetic performed on memory logical addresses shall be modulo 65,536 such thatreferences to the maximum logical address of FFFF16 plus 1 shall be to logical address000016.4.5.1.2. Memory Addressing Boundary ConstraintsThere shall be no odd or even memory address boundary constraints.4.5.2. Expanded Memory Addressing (optional)If used, then expanded memory addressing shall be performed via a memory pagingscheme as depicted in Figure 1, “Expanded Memory Mapping Diagram” [30]. Thereshall be a maximum of 512 page registers in the page file (not in logical memoryspace). These shall functionally be partitioned into 16 groups with 2 sets per groupand 16 page registers per set. Within a group, one set shall be designated for instructionreferences and the other set for operand references. The page size shall be 4096 wordssuch that one set of 16 page registers shall be capable of mapping 65,536 wordsdefined by a 16-bit logical address. The page group shall be selected by the 4-bitAddress State (AS) field of the Status Word (SW). The instruction/operand set withinthe group shall be selected by the hardware that differentiates between instruction