Supression of bottom junctions
> lower parasitic capacitance >> faster switching and/or lower power
full isolation
no latch-up
denser layout
lower interferences between the analog and digital parts of a SoC
lower losses in the passive components at high frequency
lower leakage current , enabling operation at higher temperature (250°C)
but : floating body effect in partially-depleted transistors
thin active area
lower sensitivity to radiations ( lower SEU sensitivity in memory cells )