This brief has proposed a novel algorithm along with its
mathematical formulation, including proof for address generation
circuitry of the WiMAX channel deinterleaver supporting
all possible code rates and modulation patterns as per IEEE
802.16e. The proposed algorithm is converted into an optimized
digital hardware circuit. The hardware is implemented on the
Xilinx FPGA using VHDL. Comparison of our proposed work
with a conventional LUT-based method and also with a recent
work show significant improvement on resource utilization and
operating frequency.