The latch circuit 5 is set on the rising edge of the pulse signal from the oscillator 2. Additionally, the reset pulse for the latch circuit 5 is generated immediately before the peak timing of the ramp signal Ramp3, as explained by referring to FIG. 8. That is, at least a margin M is secured from When the latch circuit 5 is reset till When it is set by the next pulse signal. The margin M is, for example, a time period during Which the ramp signal Ramp3 surely holds the ground level, and is set to a time longer than the sWitching times of the sWitches S1 and S2.