In practice, we only record the switching activities of all flip-flops and inputs and outputs of given circuits. The number of these cells is less than 1/10 of the whole number of total cells, but these cells account for most power consumptions of the processor. For other combinational cells which lack of switching activities information, we use Table I to propagate the flip-flop’s switching activity level by level to all these cells of circuits. From the table’s theory, we can find that if each flip-flop’s P and T are know, and all other combinational cells’ P and T can be calculated level by level. Using this way step by step, all cells’ switching activity can be calculated fast and easily. Therefore, the method can give a speedup for gate level simulation compared with traditional method with only small error penalty