wherein the sampling and control
periods is 100 ms, and the step size is 0.025. Fig. 14 shows the
control block diagram for the centralized inverter. A dual-loop
control scheme is used, wherein the grid currentILfis controlled
by the inner loop and the dc bus voltageVb is controlled by the
outer loop, where the phase-locked loop block is used to track
the phase of grid voltage and the unipolar sinusoidal pulsewidth
modulation (PWM) is used in the PWM block to generate four
driver signals to, respectively, drive the switchesT1,T2,T3, and
T4 in the centralized inverter. The proportional–integral controller is adopted as the inner loop controller to control the grid
currentILf,whereinKP andKI are 0.08 and 625, respectively.
Another proportional–integral controller is used in the outer
Fig. 13. Photograph of the experimental prototype. (a) PV-DCBM prototype.
(b) Centralized inverter prototype.
TABLE I I
PARAMETERS OF THEEXPERIMENTALPROTOTYPE
loop to keep the dc bus voltage Vb constant, whereinKbP and
KbI are 0.175 and 0.68, respectively.