identify those unmodified data considering the data mapping
of a cache line to DRAM chips. To this end, we propose
to add a small structure to existing caches called Chip
Write Vector (CWV). Unmodified bytes (for x8 chips) or
nibbles (for x4 chips) data can be identified by comparing
existing old data with new data being written, which will
be discussed below in detail. For simplicity of presentation,
we will use x8 DRAM chips as a default chip organization
and write-back cache case. In Figure 2, all chips except chip
#7 and chip #8 do not need to write the data of 64B cache
line. For this purpose, CWV maintains 8 bits per 64B cache
line for x8 DRAM chips. The first bit of the 8 bits indicates
whether the first chip has to be written, the second bit indicates
whether the second chip has to be written, and so on.
If at least one byte of the eight bytes going to the same chip
is modified, the corresponding bit to the chip in CWV is set
to one indicating that the chip must be written. The mechanism
of CWV for x4 DRAM chips is the same as for the x8
chip case but 16-bit CWV per 64B cache line is necessary