Synchronous and Asynchronous Design
There are two ways to build a logic circuit. One way is to have some flip-flow and registers clock in data on the rising edge of a system Clock, and other registers preset, reset, or clock as a result of new data generation. This asynchronous design. An example of this type of design is shown in. On the rising edge of the system clock, new data enters flip-flop A and cause the Q output to change, thereby clocking flip-flop B and setting flip-flop C.
The second way of building the same circuit that in this circuit all devices are clocked by the master System clock. N clocks are driven by anything other than system clocks, and present and clef inputs are not used.
There is no logical difference between these two circuits for they provide the same logic function; and if there were no such thing as propagation delay noise, both circuits would be equally desirable. This, however, is not the case
The first thing you can do to greatly improve the reliability of your system design is to write the words “no asynchronous logic permitted” in your design rules. The noise graphs help explain why synchronous design superior to asynchronous design. When the system clock's rising edge com along, many registers and flip-flops change states; these state changes cause data lines throughout the system to change. Due to propagation delays, data changes at slightly different times on data lines, creating system noise. The noise is radiated as radio-frequency energy through the power supply lines are is picked up by other system lines that act as antennas. In asynchronous case, noise is generated continuously as data ripples through the system are more flip-flops are clocked or preset (generating more noise)