As pipelines get deeper and a processor’s parallelism
increases, instruction fetch bandwidth and branch prediction
become increasingly important. To increase fetch bandwidth
and mitigate the effect of pipeline stalls for
predicted-taken branches, the PA-8000 incorporates a 32-
entry branch target address cache. The BTAC is a fully associative
structure that associates a branch instruction’s address
with its target’s address. Whenever the processor encounters
a predicted-taken branch in the instruction stream, it creates
a BTAC entry for that branch. The next time the fetch
unit fetches from the branch’s address, the BTAC signals a hit
and supplies the branch target’s address. The fetch unit can
then immediately fetch the branch’s target without incurring
a penalty, resulting in a zero-state taken-branch penalty for
branches that hit in the BTAC. To improve the hit rate, the
BTAC holds only predicted-taken branches. If a predicteduntaken
branch hits in the BTAC, the entry is deleted.
To reduce the number of mispredicted branches, the PA-
8000 implements two modes of branch prediction: dynamic
and static. Each TLB entry contains a bit to indicate which
mode the branch prediction hardware should use; therefore,
the software can select the mode on a page-by-page basis. In
dynamic mode, the instruction fetch unit consults a 256-entry
branch history table, which stores the results of each branch’s
last three iterations (either taken or untaken). The instruction
fetch unit predicts that a given branch’s outcome will be the
same as the majority of the last three outcomes. In static prediction
mode, the processor predicts that most conditional
forward branches will be untaken and that most conditional
As pipelines get deeper and a processor’s parallelismincreases, instruction fetch bandwidth and branch predictionbecome increasingly important. To increase fetch bandwidthand mitigate the effect of pipeline stalls forpredicted-taken branches, the PA-8000 incorporates a 32-entry branch target address cache. The BTAC is a fully associativestructure that associates a branch instruction’s addresswith its target’s address. Whenever the processor encountersa predicted-taken branch in the instruction stream, it createsa BTAC entry for that branch. The next time the fetchunit fetches from the branch’s address, the BTAC signals a hitand supplies the branch target’s address. The fetch unit canthen immediately fetch the branch’s target without incurringa penalty, resulting in a zero-state taken-branch penalty forbranches that hit in the BTAC. To improve the hit rate, theBTAC holds only predicted-taken branches. If a predicteduntakenbranch hits in the BTAC, the entry is deleted.To reduce the number of mispredicted branches, the PA-8000 implements two modes of branch prediction: dynamicand static. Each TLB entry contains a bit to indicate whichmode the branch prediction hardware should use; therefore,the software can select the mode on a page-by-page basis. Indynamic mode, the instruction fetch unit consults a 256-entrybranch history table, which stores the results of each branch’slast three iterations (either taken or untaken). The instruction
fetch unit predicts that a given branch’s outcome will be the
same as the majority of the last three outcomes. In static prediction
mode, the processor predicts that most conditional
forward branches will be untaken and that most conditional
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