• At least two I/O bus 8 o 16 bits (dual-channel) multiplexed are reserved for command, address, and data. As shown in the picture, more flash can be linked to at the same channel.
• Control Bus includes flash control signals (CLE, command latch enable; ALE, address latch enable; RE, read enable; WE, write enable) for each channel.
• N Chip Enable (CEx, x = 1 to N) one for each chip e N ready/busy (R/Bx, x = 1 to N), allow independent flash chip management.