Since a sequential system consists of a combination of memory and combinational logic, one approach to its implementation is to use a PAL (or other logic array described in Chapter 5) and some flip flops (for the memory). There are a variety of devices that combine a PAL and some D flip flops. One family of these devices is the 16R8,* 16R6, and 16R4. A simplified schematic of a portion of the 16R4 is shown in Figure 8.13. There are eight external inputs (two of which are shown). The registered outputs (all eight in the 16R8 and four in the 16R4) come from a flip flop, driven by a PAL (as shown for the first two outputs in Figure 8.13). Each PAL has eight AND gates (four of which are shown). There is a common clock and a common (active low) output enable, providing active low flip flop outputs (since the three-state gate inverts). Note that Q is fed back to the AND array; but, it is then provided both uncomplemented and