eight highly independent functional unit two multipliers for a 32-bit result and six arithmetic logic units. The eight functional units include instructions to accelerate the performance in video and image applications. The DM6437 also has application specific hardware logic, on- chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6437 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two [12]. The hardware set up is shown in Figure 1 and experimental set up is shown in Figure 2.