IntroductionUltrathinsolarcellsprov

IntroductionUltrathinsolarcellsprovideaneffectivewayofreducingmate-rialusage,utilizinglowqualitymaterialandrealizingdiverselikeflexibleapplications[1–3].Alongwithfabricationtechniquesforultrathincrystallinesilicon(c-Si)waferthathaveadvancedtoalevelwheredesiredthickness,roughnessandcompositioncanbereadilysynthesizedbyetchingandothertechniques[4–6],ultra-thinc-Sibasedsolarcellsespeciallythec-Si/polymerhybridoneshaveattractedalotofattention[7–12].Thisisbecausesuchc-Si/polymersolarcellismuchsuitabletorealizelowtemperatureandlargeareafabricationasitdoesnotrequireacomplexjunctionfabricationprocessanditusuallyhassimplestructures[13,14].Ithasbeenreportedthatthepowerconversionefficiency(PCE)ofultrathinc-Si/PEDOT:PSSdevicehasreached6.6%[13].WhereSharmaetalhavemadegreateffortsinfabricatinglight-trappingstructures,includingsiliconpillarsonthefront-surfaceandsilverparticlesontheback-surface,toenhancelightabsorption.Indeed,thephotocurrentdensityofdeviceshavingthesestructuresisdra-maticallyenhanced.However,thesecomplexarchitectureshavealsobroughtaboutabundantenergylosses(carrierrecombination)∗ Correspondingauthor.Tel./fax:+861061772951.E-mailaddress:mcli@ncepu.edu.cn(M.Li).duetotheincreasedinterfacedefects.Suchincreasedenergylossescanbereflectedbythefactthat,theratioofthemeasuredpho-tocurrentdensitytothetheoreticallimit(R-M/T)fordevicewithlight-trappingarchitectures(51%,18.50to36.51mAcm2)ismuchlowerthanthatofdevicewithoutlight-trappingarchitectures(76%,15.06to19.94mAcm2)[13].Additionally,thelight-trappingstruc-turesalsocomplicatethefabricationprocessthusincreasingthecost,andasaresultitisdifficulttoensuretheprocessconsistency.Fromtheaboveconsiderations,planarultrathinsolarcellsaremoresuitableforpracticalapplication.Inthiswork,wefabricatesimpleplanarc-Si/PEDOT:PSSsolarcellofabout18mthickness,whichhasgoodflexibility.Focusingonreducingthecarrierrecombination,twopassivationtechnolo-gieshavebeencarriedout.Thetwopassivationtechnologiesarenativeoxidizinganddepositingintrinsicamorphoussilicon(ia-Si)onthesiliconatthec-Si/PEDOT:PSSinterface.Thedepositingofi-a-Silayeristhebestmethod,andbycontrollingitsthicknessto2nmthePCEofdevicecanreach5.68%withR-M/Tabout83.0%.2.Experiments2.1.Fabricationofultrathinsiliconoriginally,then-type(100),doubleside-polished,4-in.siliconwafers(resistivity,1–5cm)withathicknessof500±10mwerehttp://dx.doi.org/10.1016/j.apsusc.2016.01.1290169-4332/©2016ElsevierB.V.Allrightsreserved.Y.Lietal./AppliedSurfaceScience366(2016)494–498495ultrasonicallycleanedinacetone,ethanolanddeionizedwaterfor10min,respectively.Subsequently,thesubstrateswererinsedwithdeionized(DI)wateranddriedwithanitrogengun.Afterthat,thecleansiliconwaferswereimmersedinKOHsolutionwithconcen-trationof50wt.%at90◦Cforcertaindurationoftime,toobtain18mfree-standingc-Simembranes.2.2.Siliconpassivationtheultrathinc-Siwaferisfirstcleanedbydeionized(DI)water.ThesampleswithoutpassivationweretreatedbyimmersingthesiliconwaferintoHFsolution(V:V=1:2)atroomtemperaturefor2min;thenativeoxidemethodwasdonebyplacingtheHF-cleanedwaferinadrydishwithaircondition;andtheamorphoussiliconpassivationwascarriedoutbydepositingia-SilayerontheHF-cleanedsiliconwaferusingthePECVDequipmentfor20sat250◦C.Intheia-Sidepositionprocess,a165sccmmixturegasflowofSiH4/Ar(1/24)wasused;andthechamberpressuremaintainedabout3Pa.2.3.Fabricationofphotovoltaicdevicesfirstly,theultrathinc-Siofthickness18mwascutintosmallsquaresof1×1cm2.Then,smallsiliconsquareswithoutpassiv-ation(H-terminated),withnativeoxidelayeroria-Silayerwereprepared;
highly

conductive

PEDOT:PSS

solvent

was

prepared

by

mixed

the

PEDOT:PSS

(purchased

from

Bayer

AG)

with

dimethyl

sulfoxide

(DMSO,

5

wt%)

and

Zonyl

fluoro-surfactant

(0.1

wt%).

Thereafter,

these

silicon

squares

were

tran

Introduction Ultrathin solar cells provide an effective way of reducing mate- rial usage, utilizing low quality material and realizing diverse like flexible applications [1–3]. Along with fabrication techniques for ultrathin crystalline silicon (c-Si) wafer that have advanced to a level where desired thickness, roughness and composition can be readily synthesized by etching and other techniques [4–6], ultra- thin c-Si based solar cells especially the c-Si/polymer hybrid ones have attracted a lot of attention [7–12]. This is because such c- Si/polymer solar cell is much suitable to realize low temperature and large area fabrication as it does not require a complex junction fabrication process and it usually has simple structures [13,14]. It has been reported that the power conversion efficiency (PCE) of ultrathin c-Si/PEDOT:PSS device has reached 6.6% [13]. Where Sharma et al have made great efforts in fabricating light-trapping structures, including silicon pillars on the front-surface and silver particles on the back-surface, to enhance light absorption. Indeed, the photocurrent density of devices having these structures is dra- matically enhanced. However, these complex architectures have also brought about abundant energy losses (carrier recombination) ∗ Corresponding author. Tel./fax: +86 1061772951. E-mail address: mcli@ncepu.edu.cn (M. Li). due to the increased interface defects. Such increased energy losses can be reflected by the fact that, the ratio of the measured pho- tocurrent density to the theoretical limit (RM/T) for device with light-trapping architectures (51%, 18.50 to 36.51 mA cm2) is much lower than that of device without light-trapping architectures (76%, 15.06 to 19.94 mA cm2) [13]. Additionally, the light-trapping struc- tures also complicate the fabrication process thus increasing the cost, and as a result it is difficult to ensure the process consistency. From the above considerations, planar ultrathin solar cells are more suitable for practical application. In this work, we fabricate simple planar c-Si/PEDOT:PSS solar cell of about 18 m thickness, which has good flexibility. Focusing on reducing the carrier recombination, two passivation technolo- gies have been carried out. The two passivation technologies are native oxidizing and depositing intrinsic amorphous silicon (i a-Si) on the silicon at the c-Si/PEDOT:PSS interface. The depositing of i-a-Si layer is the best method, and by controlling its thickness to 2 nm the PCE of device can reach 5.68% with R-M/T about 83.0%. 2. Experiments 2.1. Fabrication of ultrathin silicon originally, the n-type (1 0 0), double side-polished, 4-in. silicon wafers (resistivity, 1–5 cm) with a thickness of 500 ± 10 m were http://dx.doi.org/10.1016/j.apsusc.2016.01.129 0169-4332/© 2016 Elsevier B.V. All rights reserved. Y. Li et al. / Applied Surface Science 366 (2016) 494–498 495 ultrasonically cleaned in acetone, ethanol and deionized water for 10 min, respectively. Subsequently, the substrates were rinsed with deionized (DI) water and dried with a nitrogen gun. After that, the clean silicon wafers were immersed in KOH solution with concen- tration of 50 wt.% at 90◦C for certain duration of time, to obtain 18 m free-standing c-Si membranes. 2.2. Silicon passivation the ultrathin c-Si wafer is first cleaned by deionized (DI) water. The samples without passivation were treated by immersing the silicon wafer into HF solution (V:V = 1:2) at room temperature for 2 min; the native oxide method was done by placing the HF-cleaned wafer in a dry dish with air condition; and the amorphous silicon passivation was carried out by depositing i a-Si layer on the HF- cleaned silicon wafer using the PECVD equipment for 20s at 250◦C. In the i a-Si deposition process, a 165 sccm mixture gas flow of SiH4/Ar (1/24) was used; and the chamber pressure maintained about 3 Pa. 2.3. Fabrication of photovoltaic devices firstly, the ultrathin c-Si of thickness 18 m was cut into small squares of 1 × 1 cm2. Then, small silicon squares without passiv- ation (H-terminated), with native oxide layer or i a-Si layer were prepared; highly conductive PEDOT:PSS solvent was prepared by mixed the PEDOT:PSS (purchased from Bayer AG) with dimethyl sulfoxide (DMSO, 5 wt%) and Zonyl fluoro-surfactant (0.1 wt%). Thereafter, these silicon squares were tran