We present an efficient implementation of the par-allel heap data structure on a bus-based Silicon Graph- GTX/dD. Parallel heap is theoreti-cally the first heap-based data structure to have imple-mented an optimally scalable parallel priority queue on an exclusive-read exclusive-write parallel random ac-cess machine. We compared it with Rao-and-Kumar’s
concurrent heap and with the conventional serial heap accessed via a lock. The parallel heap outperformed others for fine-to-medium grains achieving speedups of two to four using six processors relative to the best se- quential execution times. The concurrent heap, how- ever, exhibited performance comparable only to the se- rial heap. As expected for coarser grain, the serial heap performed at par with or better than others.