This thesis presents the design and implementation of a Clnss-E power
amplifier implemented in 0.35 pm CMOS. The rationale behind the selection of the
final topology is discussed in detail. Cornparisons are also drawn to other potential
architectures used in practice.
Design details of both gain and output stages are also presented. Theoretical
work has been refined for use in a design setting. Many practical high-power RF
design issues have also been addressed and discussed in detail. A customized test
fixture was also devised to extract optimal performance from the amplifier.
The final amplifier implemented was a fully differential device operating at
1.88 GHz. In general. the amplifier achieved its intended design specifications
producing 185 mW with a power added eficiency of 38%.
both simulation and experimental agree well with theoretical predictions.