Chapter Outline
9.1 Introduction 227
9.2 Designing with the Two-Process PS/NS Method 228
9.3 Explanation of CPLDs and FPGAs and
State Machine Encoding Styles 231
9.4 Summary of Finite State Machine Models 234
9.5 Designing Compact Encoded State Machines with Moore Outputs 235
9.6 Designing One-Hot Encoded State Machines with Moore Outputs 237
9.7 Designing Compact Encoded State Machines with Moore and Mealy Outputs 241
9.8 Designing One-Hot Encoded State Machines with Moore and Mealy Outputs 243
9.9 Using the Algorithmic Equation Method to Design Complex State Machines 245
9.10 Improving the Reliability of Complex State Machine Designs 251
9.11 Additional State Machine Design Methods 255
Problems 262
9.1 INTRODUCTION