Figure 4 and Figure 5 give further results based on Table III-IV which show the speedup and result error percentage between the conventional method and proposed method in FIX module and FLOAT module respectively. From these figures, we can see that the gate-level power simulation speedup ratio ranges from 18.1 to 25.8, with the average of 19.9, and power analysis result error is very small. As a whole, the error percentage between the conventional method and proposed method is less than 5%, with an average 1.7 percent only. The biggest difference lies in FIX module when running Power_Max program, because the program is for largest power analysis, and the combinational logic cells has relatively high switching activities, thus resulted in 4.29% of the overall error