Local interconnecting network allows concurrent short range high-bandwidth communication between pairs of neighboring processing elements and also between processing elements and Input/Output elements.
Processing element communicates directly with one of eight neighbors which are other processing elements or I/Os and allows speed communication over short distance in this communication network.
Advantages of proposed architecture with tile organization are in simple design of elements which are arranged across the chip in uniform simple manner which secures high-level scalability of the architecture.
Decentralization of data storing, execution and control of computation results in shorter wire lengths on the chip and small latency in communication.