Because of complicated considerations in analog layout,
such as parasitic interconnect capacitance, mismatch effects,
and thermal gradients, layout synthesis in analog design flow
is the eminently critical and time-consuming [1]. One of the
most important issues in analog layout synthesis is matching.
A lot of works [2-8] have studied this topic over years, and the
major consideration of these works focus on the essential
constraints in analog placement, such as symmetry and
common-centroid constraints. The symmetry constraint
restricts devices to a mirrored placement [9]. It helps to
decrease parasitic mismatch in differential circuits. The
common-centroid constraint limits devices to a common
centroid layout structure [10], which is good for reducing
process-induced mismatches. An analog placement satisJYing
these constraints is helpful to matching. However, in addition