Where shortage of space on a PCB is an issue, for non-UL applications you may need to use the spacing smaller than those that are prescribed by IPC. However, be sure to use an ample safety factor to withstand the voltages substantially higher than the peak voltage between the traces under any abnormal and transient conditions. It is interesting to note that many major power supply manufacturers in their low-power off-line designs are widely using 500-800V MOSFETs in TO220 package operating at 400V and higher. With this package you can get about 30 mils spacing between the pads, while the documents would require at least 100 mils. Even if you spread the leads on the PWB, you can't do anything with 50-mil spacing between the TO220 leads along the surface of the package.