The system PCLK is 66.50MHz. The down-counter is
initially loaded from the Timer Count Buffer register
(TCNTBn). As soon as the down-counter reaches zero, the
timer interrupt request is generated. By calculating without
error, prescaler value, divider value, tcnt are set 94, 1, 350,
respectively. The result is as follows:
The system PCLK is 66.50MHz. The down-counter is initially loaded from the Timer Count Buffer register (TCNTBn). As soon as the down-counter reaches zero, the timer interrupt request is generated. By calculating without error, prescaler value, divider value, tcnt are set 94, 1, 350, respectively. The result is as follows:
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