FIGURE 6.-16
Counter with unused states
Ring Counter
liming signals that control the sequence of operations in a digital system can be generated by a
shift register or by a counter with a decoder ,A ring counter is a circular shift register with only one
flip-flop being set at any particular time; all others are cleared. The single bit is shifted from one
flip-flop to the next 10 produce the sequence of timing signals. Figure 6.17(a) shows a 4-bitshift register connected as a ring counter. The initial value of the register is I and requires
Preset/ Cl ear flip- flops. The single bit is shifted right with every clock pulse and circ ulates back
from T3to To. Each flip -flop is in the 1 state once every four clock cycles and prod uces one of
the four timing signals shown in Fig. 6. 17(b). Each output becomes a 1 after the negative-e detrain sit ion of a clock pulse and remains 1during the next clock cycle
the timing signals can be generated by a two- bit counter that goes through four distinct states . The de coder shown in Fig. 6 .17(c) decodes the four states of the counter and generates the required sequence of timing signals