Cache memories generally contain a tag array and a data array, shown in Fig. 1. The tag array contains the addresses of the data contained in the cache, while the data array contains the data itself. Dividing the cache into separate tag and data arrays reduces the access time of the cache, because the tag array typically contains many fewer bits than the data array and can therefore be accessed more quickly than either the data array or a single combined tag/data array. Once the tag array has been accessed, its output must be compared to the address of the memory reference to determine if a hit has occurred. Separating the cache into tag and data arrays allows the hit/miss determination to be done in parallel with some of the data array lookup time, reducing the overall access time.