Scenario two, three and four are depicted in Fig. 8. Scenario II simulates the communication between the tile interface and a link. Scenario III extends Scenario II with communication between a link and the tile interface. Scenario IV also simulates a data stream that passes the router. This scenario also gives an indication of the difference between time and lane multiplexing, because two streams will be routed to the output port East.
7. Results
The proposed circuit-switched router of this paper has been compared with a packet-switched equivalent of Kavaldjiev [6]. Both routers have bi-directional links of 16 bits. At the same frequency they have the same maximum bandwidth and bounded latency for guaranteed throughput traffic.
7.1. Synthesis Results
Both routers are synthesized in the same 0.13 μm technology. We used a TSMC low voltage, nominal VT (TCB013LVHP) standard cell library with dielectric constant (Low-k) insulators. Table 4 gives the synthesis results. Furthermore, the last column of Table 4 includes the synthesized and layouted results of the Æthereal router [5].
7.2. Power Estimation
We estimated the power consumption of our circuit switched router and the packet-switched router of Kavaldjiev using the Synopsys Power Compiler [21]. Power Compiler distinguishes between two types of power consumption: static and dynamic. The static power consumption is the power dissipated by a gate when it is not switching. The dynamic power is the power dissipated when the circuit is active. The dynamic power is composed of two kinds of contributions: switching and internal cell.