1. The time required to perform the one-time step of sorting the contents of the adjacency RAM within each PE. If we denote the maximum in-degree as d, then using a simple bubble sort, the RAM of depth d can be sorted in d(d21)/2 steps. Each step involves a compare-and-swap operation that takes 3 clock cycles. Therefore the total number of clock cycles required for sorting the adjacency RAM of depth d is 3d(d 2 1)/2. Since we have chosen the value of d as 4 in the present implementation, a constant time of 18 clock cycles is required for this one-time step.